Features
a. Single Power Supply 3.3V
b. Small Form-factor Pluggable (SFP)
c. Digital diagnostic monitor compatible
with SFF-8472
d. Compliant with ITU-T G.984.2
e. Integrated WDM filter for dual
wavelength Operate at 1490 Tx/
1310nm Rx
f. 1490nm DFB continuos-mode
transmitter
g. 1310nm burst-mode APD-TIA receiver
h. LVTTL transmitter disable input and
transmitter fault output
i. Hot pluggable capability
j. LVPECL compatible data input/output
interface
k. SC Receptacle optical connector
l. compliant with ROHS standard

Applications
Gigabit Ethernet Passive Optical Networks (GPON CLASS C++) –OLT side

a) RSSI_ACQ input signal rising edge will trigger RSSI sampling, and falling edge will trigger internal
digital RSSI information written to I2C. It is recommended that host shall not trigger RSSI_ACQ input
again until RSSI data is valid in I2C from previous RSSI trigger.
b) RSSI DDM working range is between -8 to -28dBm. RSSI DDM accuracy is better than +/-3dB for

input power level between -10 to -28dBm, the accuracy reduces to +/-5dBm to -10 dBm. If the data
pattern is at least 2^7-1 or longer, a minimum average of 8 times is strongly recommended to maintain
the RSSI reading accuracy.
 Timing Parameter Definition in Burst Mode Sequence

 EEPROM Description
The SFP serial ID provides access to sophisticated identification information that describes the
transceiver’s capabilities, standard interfaces, manufacturer, and other information. The serial
interface uses the 2-wire serial CMOS E2
PROM protocol defined for the ATMEL
AT24C01A/02/04 family of components.
When the serial protocol is activated, the host generates the serial clock signal (SCL, Mod Def
1). The positive edge clocks data into those segments of the E2
PROM that are not
write-protected within the SFP transceiver. The negative edge clocks data from the SFP
transceiver.
The serial data signal (SDA, Mod Def 2) is bi-directional for serial data transfer. The host uses
SDA in conjunction with SCL to mark the start and end of serial protocol activation. The
memories are organized as a series of 8-bit data words that can be addressed individually or
sequentially.
EEPROM Serial ID Memory Contents (A0h)

2. Note that, A0H is readable and writeable , A2H is readable and write-protected.  Monitoring Interface
The interface is an extension of the serial ID interface defined in the SFP MSA specification.
The specifications define a 256 byte memory map in E2
PROM which is accessible over a 2
wire serial interface at the 8 bit address 1010000X (A0h). The digital diagnostic monitoring
interface makes use of the 8 bit address 1010001X (A2h), so the originally defined serial ID
memory map remains unchanged. The interface is backward compatible with both the GBIC
specification and the SFP MSA. Please see Figure 1.

Pin Assignment and Function Definitions
It is the responsibility of the system integrator to assure that no thermal, energy, or voltage
hazard exists during the hot-plug-unplug sequence. It is also the responsibility of the system
integrator and end-user to minimize static electricity and the probability of ESD events by
careful design.
Pins Assignment

Notes:
1. TX Fault is an open collector output, which should be pulled up with a 4.7K~10KΩ resistor
on the host board to a voltage between 2.0V and Vcc+0.3V. Logic 0 indicates normal operation;
logic 1 indicates a laser fault of some kind. In the low state, the output will be pulled to less
than 0.8V.
2. TX Disable is an input that is used to shut down the transmitter optical output. It is pulled up
within the module with a 4.7K~10KΩ resistor. Its states are:
Low (0~0.8V): Transmitter on
(>0.8V, <2.0V): Undefined
High (2.0~3.465V): Transmitter Disabled
Open: Transmitter Disabled.
3. MOD-DEF 0,1,2 are the module definition pins. They should be pulled up with a 4.7K~10KΩ resistor on the host board. The pull-up voltage shall be VccT or VccR.
MOD-DEF 0 is grounded by the module to indicate that the module is present.
MOD-DEF 1 is the clock line of two wire serial interface for serial ID.
MOD-DEF 2 is the data line of two wire serial interface for serial ID.
4. LOS is an open collector output, which should be pulled up with a 4.7K~10KΩ resistor on
the host board to a voltage between 2.0V and Vcc+0.3V. Logic 0 indicates normal operation;
logic 1 indicates loss of signal. In the low state, the output will be pulled to less than 0.8V.
5. These are the differential receiver outputs. They are AC coupled 100Ω differential lines
which should be terminated with 100Ω (differential) at the user SERDES.
6. These are the differential transmitter inputs. They are AC-coupled, differential lines with
100Ω differential termination inside the module.

SFP Host PCB Mechanical Layout