General Description

The SFP transceivers are high performance, cost effective modules supporting  data-rate of 1.25Gbps and 20km transmission distance on 9/125µm SMF.  The transceiver consists of three sections: a FP laser transmitter, a PIN photodiode  integrated with a trans-impedance preamplifier (TIA) and DDMI control unit. All  modules satisfy class I laser safety requirements.  The transceivers are compliant with the Small Form-Factor Pluggable (SFP)  Multi-Source Agreement (MSA) and SFF-8472. For further information, please refer to  SFP MSA.

Transmitter Section  

Transmitter is designed for single mode fiber and operates at a nominal wavelength of  1310nm. The transmitter module uses a FP laser diode and full IEC825 and CDRH class  1 eye safety. The output power can be disabled via the single TX-disable pin. Logic  LVTTL HIGH level disables the transmitter. It contains APC function, temperature  compensation circuit, PECL data inputs, LVTTL TX-disable input and TX-fault Output  interface.

Receiver Section 

The receiver section uses a hermetic packaged front end receiver ( InGaAs PIN and  preamplifier). The post amplifier is AC coupled to preamplifier through a capacitor and  a low pass filter. The capacitor and LPF are enough to pass the signal from 1000Mb/s  to 1300Mb/s without significant distortion or performance penalty. The LPF limits the  preamplifier bandwidth to improve receiver sensitivity. As the input optical is  decreased, LOS will switch from low to high. As the input optical power is increased  from very low levels, LOS will switch back from high to low.

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DDMI Section 

The DDMI contains an EEPROM. It provides access to sophisticated identification  information that describes the transceiver’s capabilities, standard interfaces,  manufacturer, and other information.  The serial interface uses the 2-wire serial CMOS EEPROM protocol defined for the  FT24C02A. When the serial protocol is activated, the host generates the serial clock  signal (SCL, Mod Def 1). The positive edge clocks data into those segments of the  EEPROM that are not write protected within the SFP transceiver. The negative edge  clocks data from the SFP transceiver. The serial data signal (SDA, Mod Def 2) is  bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to  mark the start and end of serial protocol activation. The memories are organized as a  series of 8-bit data words that can be addressed individually or sequentially.  The Module provides diagnostic information about the present operating conditions.  The transceiver generates this diagnostic data by digitization of internal analog signals.  Calibration and alarm/warning threshold data is written during device manufacture.  Received power monitoring, transmitted power monitoring, bias current monitoring,  supply voltage monitoring and temperature monitoring all are implemented. The  diagnostic data are raw A/D values and must be converted to real world units using  calibration constants stored in EEPROM locations 56 – 95 at wire serial bus address A2h.  The digital diagnostic memory map specific data field defines as following.

Memory Map

Performance Specifications  

Absolute Maximum Ratings

Note: Stress in excess of maximum absolute ratings can cause permanent damage to the module  

Recommended Operating Conditions

Optical Specification

Note: 1. Minimum Sensitivity and saturation levels for a 27-1 PRBS test pattern @1.25G bps.

Electrical Specification T

Note: 2. The current excludes the output load current. 3. PECL input, internally AC-coupled and terminated.  4. Internally AC-coupled.

Diagnostics Specification

Pin Definitions  

PIN Diagram

PIN Description

Notes:  1) TX Fault is an open collector output, which should be pulled up with a 4.7k~10kΩ resistor on the  host board to a voltage between 2.0V and Vcc+0.3V. Logic 0 indicates normal operation; Logic 1  indicates a laser fault of some kind. In the low state, the output will be pulled to less than 0.8V.  2) TX Disable is an input that is used to shut down the transmitter optical output. It is pulled up within  the module with a 4.7k~10kΩ resistor. Its states are:  Low (0 to 0.8V): Transmitter on  (>0.8V, < 2.0V): Undefined  High (2.0 to 3.465V): Transmitter Disabled  Open: Transmitter Disabled  3) Mod-Def 0,1,2. These are the module definition pins. They should be pulled up with a 4.7k~10kΩ resistor on the host board. The pull-up voltage shall be VCCT or VCCR.  Mod-Def 0 is grounded by the module to indicate that the module is present  Mod-Def 1 is the clock line of two wire serial interface for serial ID  Mod-Def 2 is the data line of two wire serial interface for serial ID  4) LOS is an open collector output, which should be pulled up with a 4.7k~10kΩ resistor. Pull up  voltage between 2.0V and Vcc+0.3V. Logic 1 indicates loss of signal; Logic 0 indicates normal  operation. In the low state, the output will be pulled to less than 0.8V.  5) RD-/+: These are the differential receiver outputs. They are internally AC-coupled 100Ω differential lines which should be terminated with 100Ω (differential) at the user SERDES.  6) TD-/+: These are the differential transmitter inputs. They are internally AC-coupled, differential  lines with 100Ω differential termination inside the module.

Recommended Circuit

Package Diagram  

Board Layout Hole Pattern 

LC Interface 

Order Information